Model for capturing noise free traces for Side Channel Power Cryptanalysis based on SAKURA-G FPGA and Case study of AES

Side Channel Cryptanalysis is one of the minimum requirments for design of new cryptosystem. The main research is focused on power attack of Side Channel Cryptanalysis in which capturing of noise free traces is most important aspects.This paper presents methodology for side channel power attack based on SAKURA-G FPGA, Mixed signal oscillator, hamming distance model and statistical analysis. This method is tested with stranded cipher: Advanced Encryption Standard (AES) and recovered secret information of it. In this methodology, using SAKURA-G FPGA, captured clearly visible & noise free power traces.