Design and Implementation of HDB3 Clock Recovery Module with Large Frequency Range

With the development of the communication and information industry, the demand for high-speed data transmission is growing. One of the essential tasks of the receiver is to extract synchronization information from the received data polluted by noise and recover the data and clock accurately. Therefore, clock data recovery (CDR) is crucial in optical transmission systems and other digital transmission fields. However, the traditional bit synchronous clock recovery can only recover signals of a specific frequency. If a front-end frequency meter is added at the beginning of signal input to measure the input signal frequency, and the real-time control bit synchronization extraction circuit uses the input signal frequency as its working frequency, the operating range of the bit synchronization clock recovery circuit can be significantly improved. This will be the perfect combination of clock recovery performance and time cost. This paper studies the basic principles of bit synchronous clock recovery circuit and dynamic frequency meter. The HDB3 dynamic clock in a wide frequency range is extracted in FPGA using an all-digital design method. Through simulation and verification, the bit synchronous CDR with a pre-dynamic frequency meter has a more comprehensive recovery range, reaching 64Kb/s to 32.768Mb/s.