Design and Analysis of Multibit Multiply and Accumulate (MAC) unit: An Analog In-Memory Computing Approach

In-memory computing for multiplication operations is an approach towards mitigating the overhead caused by the migration of data between the memory and the processor observed in traditional architectures. 6T SRAMs (Static Random Access Memory) are an excellent choice for implementing this idea due to their interoperability with numerous cutting-edge processors and their compact design. In this paper, we discuss a novel method that performs in-memory dot product operations without affecting the regular processes and circuitry of the memory unit. By using current mirror (CM) circuits, the dot-product multiplication of the bits was obtained and the linearity was scrutinized and improved upon. The performance of the circuit was further examined and compared to existing designs for in-memory computation (IMC). The proposed work has an average delay of 17.07 ps and an appreciable power-delay product (PDP) of 0.01289 fJ.