Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication Systems

Venturing deeper into the outer-space has always extended the reaches of our intellect, “the farther we go, the more we know.” It has not only fostered our scientific and technological advancements but has also made us love and cherish our cozy abode in this vast universe. The knowledge gained from space missions in the guise of measurement data, is of no use if not accurately communicated back to the Earth. This work, for the first time, proposes a new VLSI architecture of turbo encoder for deep space communication systems that has been designed as per the contemporary standard specifications, recommended by CCSDS. The design has been implemented on FPGA where our turbo encoder, operates at the maximum clock frequency of 27 MHz. In addition, this paper also proposes a novel technique with an implementable architecture for simultaneous puncturing and serialization of the encoded bits, providing a 50% reduction in the overall latency over the conventional puncturing and serialization technique, consequently, aiding to achieve real-time operating capability for the designed turbo encoder system.