Low-Power High-Speed CNTFET-based 1-bit Comparator Design using CCT and STT Techniques

Carbon Nanotube Field Effect Transistor (CNTFET) based VLSI circuits are now desired due to low power and reduced chip area-which are in great demand in the VLSI realm. In this work, a design of basic 1-bit comparator circuits centered on complimentary CNTFET technique (CCT) and sleep transistor technique (STT) with chiral vector (CV=13, 0) and (CV=10, 0) is proposed. The comparative analysis of the two techniques based 1-bit comparator circuits has been presented in CNTFETs 32 nm technology. The objective is to design 1-bit comparator which helps in achieving better performance at ultra-scaled technology nodes. The results shows that the 1-bit comparator circuit using CCT based technique deliver average power (P
av
) of 832700 nW, Propagation Delay (P
d
) of 1.002 ns, Power Delay product (PDP) of 8.34×10
^-21
J and Energy Delay Product (EDP) of 6.94×10
^-27
Js. The 1-bit comparator circuit using STT based technique (CV=13, 0) deliver P
av
of 267.6 nW, P
d
of 1.002 ns, PDP of 2.68×10
^-17
J and EDP of 7.17×10
^-19
Js. The 1-bit comparator circuit using STT (CV=10, 0) technique have displayed very low average power dissipation as compared to CCT and STT (CV=13, 0). It resulted in P
d
of 1.003 ns, P
av
of 2.048 nW, PDP of 2.05×10-
¹⁵
J and EDP 4.20×10
^-15
Js and can be used in biomedical and healthcare systems.