Case Study and Analysis to Improve Power Gating Feature in SoC

This paper focuses on the study of impedance profiles of Intel SoC:'s packaging options and their impact on V
min
. In previous generations, provisions were made to short power gates in the package due to its large resistance. Recently, an improved power gate architecture was introduced with reduced resistance. Additionally, V
rel
(Voltage reliability margin) limitation was relaxed due to implementation of high density MIM caps. A study was conducted on three different package options namely, shorted core - power gate, non-shorted core-power gate and non-shorted core-power gate incorporated with high density MIM caps. Experiments concluded that non shorted power gate package incorporated with high density MIM caps helped to improve the base