Deductive Matrix Synthesis for Fault Simulation

Elements of logical vector computing are proposed, which are focused on fault simulation in digital devices. The concept of a logical vector is introduced for simulation of a single fault as addresses. For the first time the method of synthesis of deductive matrices on the logical vector of functionality is considered. The deductive matrix is used to generate tests for diagnosing a functional element and simulating faults to verify the quality of tests. A compact vector form for specifying graph structures is proposed. The advantages of fault simulation on logical vectors are shown, which lies in the high parallelism of processing faults as addresses. All models and methods are original, the validity of which is confirmed by numerous examples of the synthesis of the failure simulation matrix.