Threshold Voltage Model for 2-D FETs With Undoped Body and Gated Source

In this article, a threshold voltage model for two-dimensional (2-D) materials-based field-effect transistors (FETs) with an undoped body and a gated source is derived based on an analytical solution to Poisson’s equation at the source region. The effect of fringing fields on the underlapped region for the case when the gate has almost no overlap with the source is also studied and incorporated using conformal mapping. The derived threshold voltage model highlights the dependence of the turn-on condition on the barrier height at the metal/2-D interface, the geometry of the device, particularly on the 2-D film and oxide thickness, and the gate-to-source overlap length. Modifications on the barrier height at the metal/2-D junction due to the widely observed metal Fermi level pinning (FLP) effect on fabricated devices are also integrated. The proposed new model is verified by numerical simulations and published experimental data with close agreement.