A Comparative Analysis of HDL and HLS for Developing CNN Accelerators

In today’s world, complexity is increasing and market demands new development tools for Field Programmable Gate array (FPGA) in Convolution Neural Networks (CNN) applications. CNN involves huge number of computations. Hardware accelerators like FPGA, Graphics Processing Unit (GPU)and Application-Specific Integrated Circuit (ASIC) designs are required to speedup CNN computation. Any CNN architecture in FPGA performs better by increasing speed. This paper presents a comparative study between High Level Synthesis (HLS) and Hardware Description Language (HDL) for implementing CNN architecture in FPGA for developing hardware accelerators. In addition to Hardware Description Language (HDL), High Level Synthesis (HLS) tools are there to increase the higher abstraction level. The FPGA design turn around time is greatly reduced using HLS. High level synthesis efficiently builds and verify hardware design with less time. HLS give better control over optimization of design architecture. HLS provides greater design space exploration. HLS tool accelerates the verification time over Register Transfer Level (RTL) by increasing the abstraction level. The designed Convolution layer using Unrolling and Pipelining techniques for CNN hardware accelerator results are compared with HDL implementation using Artix-7FPGA,XC7A35T-1CPG236C.The results indicate that the HDL version is marginally superior in terms of Resource usage to the HLS implementation. HDL approach does require more programming work than its HLS counterpart. By using all available pragmas and Directives it can achieve comparable level of performance with HDL