Performance driven cell generator for dynamic CMOS circuits

A domino CMOS circuit has a highly unbalanced circuit structure in which the number of n-channel transistors is much greater than the number of p-channel transistors. This property makes it difficult to achieve an efficient layout and hence hampers the circuit's wide usage in the polycell-based design environment. The authors propose a performance-driven folding layout style for domino CMOS functional cells. The layout process consists of circuit timing analysis, transistor sizing, and automatic layout generation. It can be applied to other unbalanced circuit structures like nMOS circuits.<>