Reuse-Aware Partitioning of Dataflow Graphs on a Tightly-Coupled CGRA

We formulate a solution for the temporal partitioning of dataflow graphs (DFGs) on a coarse-grain reconfigurable array (CGRA) accelerator that is tightly coupled to system memory. The tight coupling gives rise to partitioning concerns that have not been considered in prior work. Specifically, multiple load nodes in a DFG may receive data on the same cache line, i.e., exhibit cache line reuse. Constraining such nodes to the same partition may (but not necessarily) reduce the number of memory transactions. Further, it is necessary to quantify interpartition communication by the number of memory transactions as opposed to the number of edges that cross partitions. Finally, the target CGRA accelerator imposes a limit on the number of concurrent memory transactions; a limit that must be observed. Temporal partitioning is formulated as a 01-ILP model that captures these concerns. Evaluation using 9 representative DFGs shows that: (1) the model is efficient to solve; (2) there is benefit to considering cache line reuse-memory communication cost reduces by 11% on average and by up to 20%, with a commensurate improvement in DFG throughput by 28% on average and by up to 70%; (3) the use of the number of memory transactions to quantify communication as opposed to DFG edges can reduce the number of partitions; and (4) imposing the memory transactions limit does not adversely impact the partitioning. Thus, the 01-ILP model is effective in capturing the concerns that arise and evaluation demonstrates the value of addressing these concerns.