Improved clock buffer with high PSRR for SC circuit applications

The PSRR (power-supply rejection ratio) in switched-capacitor (SC) circuits is dominated by clock feedthrough. As a result PSRR figures are typically too low for high-performance signal processing. A novel high-PSRR CMOS clock buffer, which effectively blocks this power supply (PS) noise coupling path, is presented. The circuit is a significant improvement over an earlier circuit proposed by the author (IEEE Int. Symp. on Circ. & Syst., p.68-71, May 1987), having with a simulated PSRR of over 40 dB.<>