Efficient Temporal Arithmetic Logic Design for Superconducting RSFQ Logic

In this paper, we propose a temporal decimal multiplier design that reduces the area and pin count compared to an equivalent binary multiplier. In this design, we have efficiently embedded time-to-decimal conversion inside the logic, which mitigates the need for external conversion circuits. Also, our design mitigates a drawback of temporal logic that typically requires ‘n’ time delays to represent ‘n’ numerical values, which results in longer latency for large values of ‘n’. By representing numbers as parallel temporal values where each value represents a different digit (0–9) of the number, we reduce the maximum delay needed to represent the product to only 9 delay (clock) cycles for any multiplication outcome. We show performance and area benefits for different temporal multiplier designs with fully-laid out, tapeout-ready design implemented in MITLL's SFQ5ee process. Compared to a 4-bit binary multiplier, our temporal decimal multiplier reduces the pin count by approximately 3× and the area by 40%. Finally, we evaluate our proposed temporal multiplier against conventional binary multipliers when configured for DSP and machine learning algorithms.