An Efficient and Robust Modified Hybrid Multipliers with Less Power and Better Speed

The multiplier is the building block of all arithmetic circuits, and it is widely employed in CPUs and other types of digital processing units as well as in certain kinds of integrated circuits. How quickly and how much energy a CPU uses up are indicators of its effectiveness. The multiplier circuit uses several adders, which increases the hardware complexity and hence slows down the processing and causes it to spend a lot of energy. Power efficiency and speed of the multiplier module must be drastically increased. In this study, a hybrid wallace tree multiplier of 8 bits is proposed. The central concept is to include a Single bit Hybrid Full Adder (HFA) based on the power-efficient Gate Diffusion Input (GDI) technique to create a Hybrid Array Wallace tree (HAWT) with fewer transistors and Maxresulting voltage swing. Simulated findings demonstrate significant gains over the state-of-the-art when comparing the suggested design executed in Tanner EDA at 250nm technology.