Optimization of the aspect ratio to enhance the power and noise-margin of a standard 6T(S6T)-SRAM cell

The demand for low-power, dependable and efficient static random-access memory (SRAM) design has risen as a result of the continuous progress in computational power reduction technologies. Supply voltage scaling is the preferable technique to minimize power dissipation in SRAM cells while keeping a high value of static noise margins. However, such enhancement creates several consequences, including an increase in delay and, therefore, overall high-power delay product. In this paper, a standard 6T(S6T)-SRAM cell is considered for the analysis of its performance parameters by changing the aspect ratio of the pull-up, pull-down, and access transistors for the varying supply voltage of 0.5 V to 1 V. The read/write delay, read/write power, and power delay product (PDP) are analyzed for different Cell Ratios (CR) and Pull-up Ratios (PR). This analysis helped to find the optimum power delay product for the supply voltage of 0.7 V for the 45nm technology node.