Constrained random verification of Burst operation in AXI-4

With its unique properties, AMBA AXI-4 bus interface can utilize the resources of FPGA efficiently. The latest generation of the Advanced Microcontroller Bus Architecture interface aims to give adaptability in the development of architecture's interconnection, be suited for high bandwidth and low-latency designs, enable high-frequency operation without the use of complicated bridge s.The AMBA AXI-4 system contains of master, slave and bus. During every transaction the address and data to be read or written is initialized by the master, accordingly the slave also responds. AMBA AXI-4 Master interface can support multiple masters and multiple slaves interfacing, with single master single slave talking to each other at a time. Arbiter avoids the collision, when two masters initiate the transaction at a same time [1]. A central interconnect through which the Mater and Slave are connected together, which routes requests from the mater and data is written to the slave in case of writing the data, and returning read data to the master which is requesting data, based on tags the interconnect maintains the order of reading the data [1]. For ex., Master can pipeline read requests to various other slaves. In the present work single master to single slave interfacing has been designed, where master can access the number of memory locations for reading and writing the constrained random data of different burst types. The design has been verified by performing the simulation and the results obtained have been discussed.