A reconfigurable approach to a systolic sorting architecture

A different approach to reconfigurable systolic arrays is described. In addition to making the interconnection network reconfigurable (to match the topology of the Algorithm flow graph), the authors make the individual processing elements themselves configurable, in order to provide the best match to the computational requirements of individual nodes. Rather than having a fixed instruction set, they hope to tailor the architecture of the different processing elements in such a way as to carry out their functions without the use of instruction streams. This reduces the problems of control and coordination and provides a closer match to the algorithm being implemented. The prototype architecture being developed and an analysis of its application to a particular class of problems (numeric sorting) are described.<>