Dynamic noise margins of MOS logic gates

Voltage transfer characteristics and static noise margins of basic NMOS and CMOS inverter connections are reviewed in terms of their logic dynamic performances and dynamic noise margins. The hysteresis phenomena, immunity to short pulse inputs, and noise margins depending upon both the capacitive load and the speed of the input signal are presented and discussed. The results of this study contribute to an understanding of the switching phenomena of VLSI logic and to the determining of the dynamic characteristics, including noise immunity, from well-understood static performance.<>