Board Level Probe-on-Pin Power Delivery Network Characterization

The Artificial Intelligence (AI) and High-Performance Computing (HPC) demand high power from mother board voltage regulators. It’s getting more challenging to design a robust power delivery network (PDN) to meet the voltage specifications to the processor because of the fast slew rate and large load step. Conventional power validations utilize voltage regulator testing tools (VRTTs) to mimic load transient behaviors of processors. Comparing to time domain transient results, the PDN impedance is a good frequency domain approach to ensure robust power design without applying fast load transients. This paper provides power design engineers a semi-robotic power delivery network impedance test methodology.