Module Implementation and Simulation of Timing Constraint Check Function of I2C Protocol Using Verilog

Since the Inter-Integrated Circuit (I2C) development, many efforts have been made to increase stability. The error due to the timing parameter is also one of the factors that hinder stability. In this paper, we model the I2C slave using Verilog and then perform a simple read/write operation to investigate timing parameter errors. As a solution, we present a timing parameter error detection module for the I2C protocol. The proposed module is developed based on the I2C standard mode to verify the behavior of I2C by identifying timing errors.