System Design and Prototyping for the CMS Level-1 Trigger at the High-Luminosity LHC

The high-luminosity large-hadron collider (HL-LHC) is planned to offer a very ambitious physics program, with high-precision measurement and evaluation of the standard model (SM), and motivate the searches for new physics. The efficient data collection and precise events reconstruction in the harsh environment of 200 proton–proton interactions are vital for achieving the success of the HL-LHC program. To realize these requirements, the compact muon solenoid (CMS) detector has planned to completely replace the data acquisition (DAQ) and trigger system. The CMS Level-1 trigger system will handle the enormous detector input bandwidth of 63 Tb/s with a maximum output rate of 750 kHz and is desired to complete the processing within $12.5 \mu \text{s}$ . For this purpose, CMS has planned to replace the Phase- $1 \mu $ telecommunications computing architecture (TCA)-based processor boards and crates an advanced TCA (ATCA) form factor. Each ATCA board will host Xilinx large UltraScale/UltraScale+ family field programmable gate arrays (FPGAs) and support more than a hundred high-speed optical links ( $\sim $ 28 Gb/s), capable of meeting the high bandwidth and processing requirements of HL-LHC. Along with the advancement in hardware, the Level-1 trigger system will employ highly modular, flexible, and adequately sophisticated algorithms that were only possible in offline reconstruction, such as the particle-flow (PF) algorithm. The modular and flexible architecture will help address the HL-LHC dynamic physics requirements. We will discuss the details of system design, prototyping, and the algorithms employed for the Level-1 trigger system.