Efficient modeling of interconnections in a VLSI circuit

An efficient method is presented for modelling the parasitic capacitance of interconnections in a VLSI circuit. The method is three-dimensional and based on a combination of the Green's function method and a recently proposed technique for inverting partially specified, positive definite matrices. It yields a reduced yet accurate model and requires O(s) time and O( square root s) storage, where s is the size of the layout.<>