FPGA Implementation of Systolic FIR Filter Using Single-Channel Method

High-performance Finite Impulse Response (FIR) filters are required by numerous industries, including image processing, digital signal processing, communications, and many more. To approach FPGA based on Systolic FIR designs, this study uses a single-channel method with coefficients being symmetrical to achieve quick responsiveness and the ideal area. The filter design’s outcome is accomplished on the reconfigurable hardware platform by the exact operations performed by the multiply-accumulator (MAC) integrated Digital Signal Processing (DSP) blocks. The synchronization, consistency, and modularity required to develop the ideal filter configuration are provided by systolic FIR architecture. Its pipeline architecture also provides excellent throughput, and its symmetrical approach reduces the memory footprint. Both methods enhance the FIR design’s overall performance in the FPGA space. The Virtex-5 FPGA board was used to implement the suggested FIR architecture once it had been satisfactorily validated by the Xilinx ISE 14.7 tool. Comparing the design process to older architectures, it exhibits a significant gain in maximum operating frequency and space savings