An Architecture of a True Single Phase Clock D Flip-flop utilizing 45nm Technology

In this paper, we present the details of a high-speed, double-edge-triggered D-flip-flop with low power consumption and True Single Phase Clocking. With the TSPC CMOS flip-flop, the clock skew is completely removed, and only one clock signal is required. Because the original TSPC flip-flop is so sensitive to the clock slope, and because so much energy is wasted pre-charging the internal nodes, TSPC dynamic circuits are notoriously inefficient. High leakage current is increasingly contributing to power dissipation in traditional CMOS designs. As a solution to the leakage problem plaguing conventional CMOS TSPC D flip-flops, this study employs Multi-threshold CMOS technology. With the help of MICROWIND 4.1 's simulation features, we can examine how the designed flip-flops fare in terms of power consumption, propagation delay, and power delay product. The static power consumption of the proposed MTCMOS designs, such as the original MTCMOS implementation and the NMOS insertion in MTCMOS design of TSPC D flip-flop, is reduced by 57.517^% and 58.871%, respectively, when compared to the static power consumption of the conventional DE- TSPC D flip-flop operating at 1.2V.