Design and Implementation of MAC by Using Efficient Posit Multiplier

In latest times, Posit number format proposed instead of IEEE 754.2008 number format is yielding better and accurate results in dynamic and extensive range of applications. Due to its non uniform distribution case, this number format is paving its way in many modern applications. Multiply Accumulate (MAC) unit implementation along with the efficient Posit multiplier is not designed in any of the recent studies but adder and multiplier designs in separate have been proposed and implemented. To use the posit number system effectively in many of the modern applications, MAC design implementation along with the efficient posit multiplier is proposed. The flexible nature of posit number when compared to IEEE 754.2008 is that posit number can have any number in exponent bit width and total bit width. Hence parameterization of all data path bit widths is proposed and the designing is implemented in VHDL. The code that is obtained is combinational design. The area, power and delay obtained on different conditions were studied, analyzed and provided.