A Proposal for Programmable Pattern Generator and its FPGA implementation

The pseudo random sequences generated from the Linear Feedback Shift Register (LFSR) can be used to construct in Built-In Self-Test (BIST) modules as well as for cryptographic applications. Accounted as the structured method of self-testing for an IC, BIST is a must for mission critical applications such as medical and automotives. One of the major components of BIST is pattern generator block which supplies required patterns for testing the quality and performance of a circuit under test. Quality of testing is also decided by the number of faults detected by these patterns supplied by the pattern generator. A pattern generator which can supply a better range of patterns is more efficient and preferred as a large number of faults can be covered. Our work focusses on designing a pattern generator designed in the platform of an LFSR and leverages the different circuit structures based on a characteristic polynomial. The proposed pattern generator can generate patterns based on any degree of polynomial and for any LFSR structure Galois, Fibonacci, complete or reseeding thus enabling this circuit to be suitable for pseudorandom, pseudo exhaustive or exhaustive in the case of circuits with few inputs. The FPGA implementation is done in BASYS 3 board and ASIC implementation using Cadence Genus tool.