Disturb-Free Operations of Multilevel Cell Ferroelectric FETs for Nand Applications

We have experimentally investigated disturb-free operations of multilevel cell (MLC) ferroelectric field-effect transistors (FeFETs) in a NAND array. The fabricated FeFET cells are systematically characterized, and optimized schemes to write FeFET cells into multiple states with high stability are investigated. Write and read schemes to achieve stable MLC operations of FeFET NAND arrays are proposed. For the realization of disturb-free MLC operations, both program and read disturbs are systematically characterized at the array level. In addition, margins of program inhibition voltage (
${V}_{\text {inhib}}{)}$
and pass voltage (
${V}_{\text {pass}}{)}$
are determined from the measurement results. This work provides a fundamental understanding of disturb-free MLC FeFET operations for NAND applications.