Actual Reasons Involving Turn-Off Losses Improvement With Increasing Load and Gate Resistance in MOSFETs Enhanced With Kelvin Source

This article explains the actual reasons behind the improvement in terms of turn-
off
energy losses (Eoff) reduction, obtained using Kelvin pin (4-lead, 4L)
mosfet
s instead of 3L ones. Eoff increases by increasing gate resistance and load, but the experimental results reveal that the increment is less in 4L than in 3L
mosfet
s. Analyzing the turn-
off
waveforms and adopting circuit analysis, the article first proves that the common argument about the undesired effect of the parasitic source inductance in 3L
mosfet
s is misleading. Then, the reasons behind the aforesaid improvement in 4L
mosfet
s with increasing gate resistance and load are described by means of the derived analytical expressions. Finally, the analysis of the equations has provided helpful information at the design stage, also accounting for the different device technologies. In particular, the improvement obtained using 4L
mosfet
s reduces as the driving loop parasitic inductance increases and evanesces if its value becomes comparable with the power loop parasitic inductance.