Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

With transistors scaling down to 3 nm node and beyond, short channel effect (SCE) as well as power consumption dissipation present immense challenges for further scaling down of the transistor. Hence the Gate all around field effect transistor (GAA-FET) is proposed to replace the Fin field effect transistor (FinFET) in 3 nm technology node and beyond due to its better gate control over the channel with surrounding gate structure, thus providing improved SCE constraint ability. Traditional transistors suffer from the problems of “Boltzmann Tyranny” and cannot overcome the subthreshold swing (SS) limit of 60 mV/dec at room temperature. To maintain high
$I_{on}$
and avoid
$I_{off}$
from increasing too much, supply voltage (
$V_{DD}$
) of the conventional transistor cannot scale down proportionally with the dimension of the transistor. The concept of negative capacitance (NC) has been demonstrated to be able to obtain sub-60 mV/dec SS with the ability of amplifying the potential of the channel region without
$V_{DD} $
increment. The novel device structure of negative capacitance gate all around field effect transistor(NC GAA-FET) can combine both the advantages of GAA-FET and NC-FET, and is the most promising ultra-low power consumption device and promises to sustain the Moore’s law further beyond what is predicted now. Whereas, according to our knowledge, there have been few review papers about NC GAA-FET till now. Herein, we summarize the recent developments of the NC GAA-FET both in simulation and experimental aspects, which we believe will bring about profound changes to the further development of NC GAA-FET devices.