Realization of Turbo Decoder on Coarse Grained Reconfigurable Architectures

Error correcting codes such as turbo codes are incorporated in present-day wireless and satellite communication systems for error free data transmission. Conventional turbo decoders use the MAP algorithm to achieve near Shannon limit performance. Many hardware implementations of turbo decoders are carried out on FPGAs. But there is inefficiency in the realization of such complex designs with respect to area and power compared to that of ASICs. This work highlights the realization of a turbo decoder on coarse grained reconfigurable architectures (CGRAs)- a new class of programmable hardware that amalgamates the advantages of both ASICs and FPGAs. For the modelling, exploration and implementation of such architectures, hardware designers have developed many platforms. In this work,the realization of complex iterative loops of turbo decoder on CGRAs, are carried out using CGRA-ME framework, thus eliminating the complexity involved in its FPGA equivalent. The turbo decoder benchmark is implemented on ADRES and flavours of Simple CGRAs. The corresponding configuration bitstreams and the Verilog HDLs generated, are used to perform the area and power analysis. The decoder implemented on ADRES results in the reduction of area by 15.48% and 35.21% compared to that of Simple diagonal and Simple orthogonal respectively. The net power consumed by Simple orthogonal is less in comparison to Simple diagonal by 41.68% and with that of ADRES by 6.36%.