A 62-GHz High-Efficiency Power Amplifier With Modulation Capability via Back-Gate in 22-nm FD-SOI

This letter presents a feasibility study for a 62-GHz power amplifier (PA) in a 22-nm CMOS technology with integrated data modulation via the back-gate. The proposed PA consists of two pseudo-differential cascode stages and provides a peak gain of 23.3 dB, a Psat of 13.6 dBm, and a peak power-added-efficiency (PAE) of 28.3%. The PA consumes 96 mW from a 2-V
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DD at its saturation. Thanks to the transistor back-gate, the PA can be dynamically switched on and off by increasing the threshold voltage through the back-gate. This avoids ac ground, gain, and stability problems caused by conventional front-gate switching. In off-mode, it draws 2.5% of its peak dc power. Rise- and fall-times of 1 ns were measured. The possibility of back-gate-based modulation was experimentally demonstrated, showing that the PA can be used as a single-device transmitter. Compared to previously reported works, the PA shows one of the highest PAE and excellent linearity. To the best knowledge of the authors, this is the first investigation of a 60-GHz PA with data modulation via the back-gate.