Digital VLSI architectures for neural networks

A generic iterative model is proposed for a wide variety of artificial neural networks (ANNs): single-layer feedback networks, multilayer feedforward networks, hierarchical competitive networks, and some probabilistic models. A unified formulation is provided for the retrieving and learning phases of most ANNs. On the basis of the formulation, a programmable ring systolic array is developed. The architecture maximizes the strength of VLSI in terms of intensive and pipelined computing and yet circumvents the limitation on communication. It can be adopted as a basic structure for a universal neurocomputer architecture.<>