Comparative analysis of low power leakage techniques implemented in different CMOS VLSI Circuits

Scaling is necessary with the advancement of technology in VLSI circuits. With scaling increment in sub-threshold leakage current by minimizing the threshold voltage, enhancement of tunneling leakage current with thinning of gate oxide a creates problem. Therefore, a reduction in leakage power becomes essential for the sustainment of scaling in the CMOS process. Multiple leakage low power reduction techniques are developed to cope up with this problem. Basic gates have been implemented by various researchers with these techniques at 45nm technology nodes and leakage power has been estimated. In this work different power reduction techniques are first explained, and work done utilizing these techniques in reducing average power dissipation has been compiled at 45nm technology nodes for a basic NAND gate and a Current Starved VCO. This comparative analysis will improve the selection process among various available techniques for different applications. Power delay products are also compared in this work which helps in deciding for the applications wherever a trade-off is required between delay and power dissipation.