Reconfiguration algorithm of fault-tolerant two-dimensional VLSI arrays

The authors propose a general reconfiguration algorithm of two-dimensional arrays to achieve yield enhancement. The algorithm is general in the sense that it can be applied to any of the two-dimensional arrays ranging from as small as memory arrays to as complex as processor arrays where each cell is likely to occupy a complete chip for its implementation. The time complexity of the proposed optimal reconfiguration algorithm is o(N/sup 2/) to reconfigure a potentially faulty N*(N+SC) physical array into a fault tree N*N logical array, where SC is the number of spare columns.<>