AI-Accelerator Proof of Concept by a Multi-IP Chip Project

In this paper, a multi-intellectual-property-core (multi-IP) chip project of AI-Chip Design Center (AIDC) is reviewed. AIDC is a joint project of National Institute of Advanced Industrial Science and Technology (AIST) and the University of Tokyo, aiming at supporting the proof of concept of domain specific accelerators for AI applications of start-up companies. In the multi-IP chip project, participant start-up companies implement their own accelerator IPs combining with the platform, which is consisting of CPU s and interfaces such as LPDDR, UART, PCIe and so forth, through the AXI-bus based network on chip (NoC). AIDC releases this platform with design-and-evaluation environment and arranges the silicon verification. Further reduction in turnaround time (TAT) and non-recurring engineering (NRE) cost in the practical business is also discussed.