Emitter injection control in LVTSCR for latch-up free ESD protection

A low-voltage triggered silicon controlled rectifier with optimized holding voltage for ESD protection, has been developed and is demonstrated in a 0.18 /spl mu/m CMOS technology. Process and device simulation is used to determine the relationship between electrical parameters and geometrical features. Pulse measurements of silicon test structures demonstrate that the ESD efficiency of this approach is 3-5 times that of a conventional grounded gate snapback n-MOS with the same holding voltage.