VLSI design of inner-product computers using distributed arithmetic

Methods for designing custom VLSI implementations of distributed arithmetic architectures are studied. Inner product computations where one vector is fixed form the basis of many digital signal processing algorithms. The bit- and word-level partitioning of the inner product allows a mapping to a distributed arithmetic computation which uses table-accumulator structures instead of multipliers. The distributed arithmetic computation can be expressed as a regular iterative algorithm which can be mapped to space-time coordinates producing a regular VLSI implementation. The partitioning and mapping of the inner product computation provide a systematic method for searching a large design space for optimal architectures. Optimality is defined in terms of cost expressions and constraints that are functions of area, latency, period and precision.<>