SOI devices for sub-0.1 /spl mu/m gate lengths

Different SOI MOSFET structures for sub 0.1 /spl mu/m gate lengths are discussed. To reduce short-channel effects such as DIBL (drain induced barrier lowering) and subthreshold slope degradation, thin SOI films have to be used, which causes high source and drain resistance and low threshold voltage problems. These problems can be solved using midgap gate materials, elevated or Schottky S and D structures and multiple gates. The use of ground-plane structures improves the short-channel effects but increase the body effect, while the use of multiple gates (double gate, triple gate, etc.) improves all device characteristics and increase the current drive. SOI seems well adapted to future low-power VLSI electronics.