A pipelined, expandable VLSI sorting engine implemented in CMOS technology

An improved implementation of the rebound sorter of T.C. Chen et al. (IEEE Proc. 4th Conf. of Very Large Databases, p.312-18, Sept. 1978) is described. The pipelining technique chosen is unique to this design. A single rebound sorting chip can sort eight 16-b records. By connecting these chips in a chain, it is possible to sort more than eight records. The VLSI version of the rebound sorter described in this paper is also simpler and smaller than many other sorters discussed in the literature. The Genesil silicon compiler, a commercial CAD tool, was used to implement the chip.<>