The ICAP parallel processor communications switch

The architecture of a custom VLSI parallel communications switch (PARCOS) chip is described. The PARCOS chip consists of a communication matrix of 32-b serial inputs and 32-b serial outputs and an on-chip control memory. The control memory, called the connection pattern cache (CPC), is constructed so that PARCOS can hold up to 32 of the most frequently used connection patterns between its inputs and outputs. Any of these stored patterns is incrementally modifiable, and the connection pattern of the communication matrix can be switched from one stored pattern in the CPC to another, with a single instruction. This chip is used in building an easily reconfigurable, circuit-switched connection network for the interprocessor communication of the intermediate-level processors of the Image Understanding Architecture (IUA) prototype.<>