A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods

Data-retention flip-flops (DR-FF) provide an efficient state retention capability for any processor with frequent active-to-sleep mode transitions. This brief proposes new ultra-low-power balloon-based DR-FFs operating over a wide supply voltage range achieving a sleep mode power consumption as low as 380fW, an improvement of
$185\times $
over the previously reported CMOS DR-FFs. The proposed DR-FFs have significantly lower transition mode energy consumption compared to prior-art non-volatile DR-FFs (>
$18\times$
). The proposed DR-FFs consume the lowest total energy (sleep, store and restore modes) for sleep mode times less than 520 ms. Additionally, the designed DR-FFs are comparable with most of the NV-FFs in literature for sleep times of up to 100 s, while eliminating the drawbacks of Non-volatile data retention FFs (higher/multiple supplies, integration/endurance issues).