A 3D Stackable DRAM: Capacitor-less Three-Wordline Gate-Controlled Thyristor (GCT) RAM with >40 μ A Current Sensing Window, >1010 Endurance, and 3-second Retention at Room Temperature

3D stackable DRAM was highlighted as a promising R&D path to continue DRAM scaling beyond planar structure [1]. In this work, we propose a novel capacitor-less three-wordline gate-controlled thyristor (GCT) RAM that shows excellent large hysteresis Vt window $\gt 2\text{V}$, large sensing current window $(\gt 40 \mu \text{A}$ or even up to $60 \mu \text{A}$ between “0” and “1”), good retention $(\sim 3 \sec$ at room-temperature) as compared with standard DRAM $(\sim 64$ msec refresh), and no degradation within $10 ^{10}$ cycling endurance test (forecasted to be nearly unlimited endurance). The GCT RAM uses 3-WL gate bias to electrically control the virtual junction concentration of “P-N-P-N” device in the GAA structure to facilitate the thyristor-mode “latch-up” hysteresis effect and enable excellent RAM operation window. It’s different from the conventional thyristor RAM that counts on difficult physical junction doping control. We propose a 3D stackable configuration that leverages the processing of the stacked nanosheet CMOS and 3D stackable NAND Flash to realize a highly layer-stackable 3D DRAM architecture. Successful array selection methods are demonstrated. It opens a new potential path for 3D DRAM.