Vector-Deductive Memory-Based Transactions for Fault-As-Address Simulation

The main idea is to create logic-free vector computing, using only read-write transactions on address memory. The strategic goal is to create a deterministic vector-quantum computing using photons for read-write transactions on stable subatomic memory elements. The main task is to implement new vector computing models and methods based on primitive read-write transactions in vector flexible interpretive fault modeling and simulation technology, where data is used as addresses for processing the data itself. The essence of vector computing is read-write transactions on vector data structures in address memory. Vector computing is a computational process based on elementary read-write transactions over cells of binary vectors that are stored in address memory and form a functionality where the input data to be processed is the addresses of these cells. A metric-axiom of convolutional closure of cyclic distances between n objects into the 0-space is introduced. A model of xor-relations between wonderful logical functions
$(\mathbf{and}\oplus$
or
$\oplus$
xor
$=0)$
of digital circuits is proposed; it is convoluted into zero-space, which makes it possible to solve problems of technical diagnosis, generative machine learning, similarity-difference search between processes and phenomena. A failure-driven management metric
$\mathbf{T}\oplus \mathbf{F}\oplus \mathbf{L}=0$
is introduced, which formalizes all known processes for creating computing, including design and test, cyber-physical and cyber-social computing, federated and generative ML-computing. The equation of logical analysis is introduced
$\mathbf{S}\oplus \mathbf{D}=\mathbf{a}\cup \mathbf{b}=\mathbf{U}$
, which makes it possible to calculate the similarity-difference between objects by means of parallel logical procedures on binary vectors that form the U-universe. The advantages of a vector universal model for a compact description of ordered processes, phenomena, functions, and structures are defined for the purpose of their parallel analysis. Analytical expressions of logic, which require algorithmically complex calculators, are replaced by output state vectors of elements and digital circuits, focused on the parallelism of register logical procedures on regular data structures. A vector-deductive method for formula synthesis for propagating input lists (data) of faults is proposed, which has a quadratic computational complexity of register operations. A new matrix of deductive vectors has been synthesized, which is characterized by the following properties: compactness, parallel data processing based on a single read-write transaction in memory, elimination of traditional logic from fault simulation procedures, full automation of its synthesis process, and focus on technological solving all problems of technical diagnosis. A new structure of the vector deductive fault simulation sequencer is proposed, which is characterized by easily implementation on a single memory block, eliminates any traditional logic, uses data read-write transactions in memory to generate an output fault vector, uses data as addresses to process the data itself.