Cross Layer Design Using HW/SW Co-Design and HLS to Accelerate Chaining in Genomic Analysis

DNA sequence analysis is a computationally intensive task. Minimap2 is a state-of-the-art software tool for third-generation sequence analysis workflow. Nearly 50% of Minimap2’s computation time is spent on what is known as the chaining step. In this article, the chaining step is accelerated using a novel heterogeneous computing system combining an Intel FPGA-based hardware accelerator and a CPU (using high-level synthesis for the FPGA and multithreaded software for the CPU). The system in this article is capable of handling large-realistic workloads and achieves up to
$\sim 1.35\times $
performance improvement over the software solution running on an Intel CPU with SIMD intrinsics (Intel’s latest AVX-512) while consuming
$\sim 27\%$
less energy. When compared to the software solution running on the CPU without SIMD intrinsics, the system performs
$\sim 1.9\times $
faster while consuming
$\sim 38\%$
less energy. Importantly, this work also ensures that the accuracy of the output generated is not compromised for the speed-up gained (this work only has an error rate of less than 10−6% compared to 26% in previous FPGA-based chaining step accelerator).