Optimization of Slew Mitigation Capacitor in Passive Charge Compensation-Based Delta–Sigma Modulator

In this brief we propose a scheme of optimizing the size of charge compensation (CC) capacitor in a delta-sigma modulator (DSM) using a passive charge compensation (PCC) based switched capacitor integrator (SCI). The slewing behavior of a PCC based SCI is analyzed in both integration phase (IP) and sampling phase (SP) to optimize the size of CC capacitor. The effectiveness of the proposed scheme is demonstrated by implementing a 2–1 cascaded DSM using PCC based SCI with optimized value of CC capacitor in 0.18-
$\mu \text{m}$
CMOS technology. The DSM operates at a frequency of 5-MHz and achieves a peak SNDR of 103.1-dB in the audio bandwidth of 20-kHz. The power consumption of DSM is 220-
$\mu \text{W}$
at a supply voltage of 0.85-V and it consumes 1.3 mm2 of area. Post-layout simulations show an improvement of 10.8-dB in the SNDR of DSM by using the optimized value of CC capacitor in PCC based SCI.