Inductively-Coupled High-Speed Interconnects of 3D-Integrated CMOS Image Sensors

This paper presents a high-speed interconnect of 3D-integrated backside-illuminated (BSI) CMOS image Sensor (CIS) chip by inductive coupling link. With the CIS fusion oxide bonding process, the two stacked chips are able to be planted face to face, reducing the interconnect distance to 5um, which benefits for diminishing the channel insertion loss through inductive coupling. With a proper impedance matching network, the simulated insertion loss of the inductive coupling channel can be as low as -1.1dB. Schemes of inductive coupling links, either with or without carrier waves are compared. A $4 \times 4$ coupling array enables a data rate of 80Gb/s (5Gb/s per channel), corresponding to an area efficiency of 270Gbs/mm
²
. This scheme offers a realizable low-cost high-speed solution for BSI-CIS 3D integration.