Voltage Detection Circuit with Delay for Power Management Circuits

Power management circuits that have stable output voltage can provide reliable power supply for other circuits and chips. However, in some cases, the magnitude of the power supply may fall below a threshold voltage, which has a negative effect on its load circuit. This paper presents a voltage detection circuit with delay for monitoring the output voltage of power management circuits, which can detect an undervoltage condition on the output voltage and generate a power-on reset (POR) signal with a delay time that can be set. The delay time generator only works within the setting delay time, thus, the quiescent current consumption can be reduced and then the efficiency of the power management will be improved. The voltage detection circuit with delay is implemented in a $0.18 \mu \mathrm{m}$ CMOS process with an active area of 0.039 mm², operating in the voltage ranging from 1.8 V to 3.3 V. The proposed circuit consumes 3.3 $\mu \mathrm{A}$ of quiescent current during the setting time and 1.55 $\mu \mathrm{A}$ of quiescent current when the oscillator and the timer do not work. The threshold voltage is 95% of the output voltage and the delay time is set to 20 ms.