Implementation of LFSR based Fast Error-Resilient Ternary Content-Addressable Memory

Memories are the major building blocks for various applications, which includes integrated circuits, digital circuits, digital equipment. The conventional memories are developed using Static Random Access Memory (SRAM) cells. However, they are facing the memory read-write synchronization issues, and stuck at faults with high errors. Therefore, this article is focused on implementation of Error-Resilient Ternary Content-Addressable Memory (ER-TCAM) for fast data storage with high speed read-write operations. Here, Linear Feedback Shift Register (LFSR)s were introduced for generating the random pattern sequences with address synchronization properties. Finally, LFSR based ER-TCAM provided the optimal data storage with high self-error detection, correction properties. The simulations revealed that the proposed method resulted in better area, delay, power performance as compared to conventional approaches.