Power Supply Variations and Analog Performance of 5-nm Node Silicon Nanosheet Transistor

This work estimates the possible changes in analog performance due to on-chip power supply variations for a 5 nm node N-channel Nanosheet Transistor. A fully calibrated Sentaurus TCAD model is used for this purpose. On-chip supply voltage, in real life, suffers from unwanted ripples significantly affecting different analog parameters. For 25 mV of peak-peak ripple voltage and nominal supply voltage of 0.7 V: the maximum gm value can be 1.7% smaller or 1.6% larger; the minimum
$g$
ds value can increase by 4% or decrease by 4.9%; the Av value can be more significant by 6.85% or smaller by 5.47%; the f
T
value can degrade by 1.24% or improve by 1.4%; the GFP value increase by 5.5 % or decrease by 4.2%; and the t
d
value varies by up to 3.56% or -3% from the nominal value.