By Topic

IEEE Micro

Issue 2 • Mar.-Apr. 2014

Filter Results

Displaying Results 1 - 14 of 14
  • [Front cover]

    Publication Year: 2014, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (6401 KB)
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2014, Page(s): c2
    Request permission for commercial reuse | PDF file iconPDF (555 KB)
    Freely Available from IEEE
  • [Masthead]

    Publication Year: 2014, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (574 KB)
    Freely Available from IEEE
  • Hot Chips and Other Themes

    Publication Year: 2014, Page(s):2 - 3
    Request permission for commercial reuse | PDF file iconPDF (1289 KB) | HTML iconHTML
    Freely Available from IEEE
  • Hot Chips 25

    Publication Year: 2014, Page(s):4 - 5
    Request permission for commercial reuse | PDF file iconPDF (1081 KB) | HTML iconHTML
    Freely Available from IEEE
  • Haswell: The Fourth-Generation Intel Core Processor

    Publication Year: 2014, Page(s):6 - 20
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3279 KB) | HTML iconHTML

    Haswell, Intel's fourth-generation core processor architecture, delivers a range of client parts, a converged core for the client and server, and technologies used across many products. It uses an optimized version of Intel 22-nm process technology. Haswell provides enhancements in power-performance efficiency, power management, form factor and cost, core and uncore microarchitecture, and the core... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Software Engineering for the 21st Century

    Publication Year: 2014, Page(s): 21
    Request permission for commercial reuse | PDF file iconPDF (973 KB)
    Freely Available from IEEE
  • Kabini: An AMD Accelerated Processing Unit System on A Chip

    Publication Year: 2014, Page(s):22 - 33
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2453 KB) | HTML iconHTML

    The AMD accelerated processing unit (APU) code-named "Kabini" integrates a quad-core CPU and a fully featured GPU. It is the first APU generation to incorporate a complete system-on-a-chip (SoC) IP to provide power efficiency and a small footprint. The device family includes the ultra-low-power optimized SoC codenamed "Temash," which is targeted for tablet and two-in-one detachable PC use. Kabini ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hexagon DSP: An Architecture Optimized for Mobile Multimedia and Communications

    Publication Year: 2014, Page(s):34 - 43
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2541 KB) | HTML iconHTML

    Heterogeneous computing is essential for mobile products to meet power and performance targets. The Qualcomm Hexagon DSP, now in its fifth generation, is used for both modem processing and multimedia acceleration. By offloading multimedia tasks such as voice, audio, sensor, and image processing from the CPU to the DSP, Hexagon achieves significant power savings. Hexagon features a unique architect... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The Xbox One System on a Chip and Kinect Sensor

    Publication Year: 2014, Page(s):44 - 53
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2952 KB) | HTML iconHTML

    The system on a chip (SoC) at the heart of the Xbox One entertainment console is one of the largest consumer designs to date, with five billion transistors. The Xbox One Kinect image sensor uses time-of-flight technology to provide high-resolution, low-latency, lighting-independent 3D image sensing. Together, Kinect and the SoC provide unique voice and gesture interaction with high-performance gam... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Process and Circuit Optimization for Power Reduction Using DDC Transistors

    Publication Year: 2014, Page(s):54 - 62
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1146 KB) | HTML iconHTML

    The Deeply Depleted Channel (DDC) transistor architecture offers 2 to 3 times improvement in body coefficient and 60 percent improvement in local mismatch in 55-nm technology, extending design techniques such as body biasing with voltage scaling to more recent technology nodes. This article presents a body bias architecture for adaptive correction of manufacturing variation, with less than 0.5 per... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The Fault Lines along Fast Lanes

    Publication Year: 2014, Page(s): 64
    Request permission for commercial reuse | PDF file iconPDF (160 KB) | HTML iconHTML
    Freely Available from IEEE
  • Rock Stars of Mobile Cloud [Advertisement]

    Publication Year: 2014, Page(s): c3
    Request permission for commercial reuse | PDF file iconPDF (2247 KB)
    Freely Available from IEEE
  • Membership Matters [Advertisement]

    Publication Year: 2014, Page(s): c4
    Request permission for commercial reuse | PDF file iconPDF (1732 KB)
    Freely Available from IEEE

Aims & Scope

IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center